Modern wireline communications systems often employ integrated circuits (ICs) embodying transmitters and receivers that communicate with differential signalling over copper traces on printed circuit boards (PCBs).
Differential signalling is employed to increase immunity to noise. A differential signalling scheme applies a pair of complementary signals across a pair of signal wires, such that the information content is contained only by the difference in the signal between the wires. Since external interference tends to affect both wires in the pair similarly, this scheme tends to improve resistance to electromagnetic noise compared with signalling schemes that employ a single wire containing the information content and an unpaired reference ground.
The receiver may receive a transmission from a transmitter with different operating point characteristics, whether or not manufactured by a different entity. Different architectures of the circuits, and/or the absence of a common reference ground between the transmitter and the receiver means that a differential signal generated by the transmitter may have different electrical characteristics from the differential signal expected to be received by the receiver, including their respective DC operating points.
The potential disparity between the electrical characteristics of the transmitter and the receiver may be alleviated, in some example cases, by isolating the DC condition of the receiver from that of the transmitter.
In some example cases, this may be achieved by interposing a discrete capacitor on one of the PCBs between the transmitter and the receiver, such as is shown in FIG. 1. A transmitter IC 10 comprises at least one transmitter circuit Tx(i) 11i (only a first Tx(a) 11a and last example Tx(m) 11lk of which are shown, with ellipses denoting others for ease of illustration—the “i” referring to any one of these in the range of a . . . k), employing differential signalling across respective differential signalling pairs of transmit signal traces (Tx(i)p 12ip, Tx(i)m 12im), where subscript p denotes the positive differential signal and subscript m denotes the minus differential signal, that connect to respective copper traces 22ip, 22im, on a PCB 20. Each transmit signal trace Tx(i)p 12ip, Tx(i)m 12im has a corresponding transmit termination resistor RTXip 13ip, RTXim 13im at a back end of the transmitter IC 10.
Similarly, a receiver IC 30 comprises at least one receiver circuit Rx(i) 31i, employing differential signalling across respective differential signalling pairs of receive signal traces (Rx(i)p 32ip, RX(i)m 32im) that connect to respective copper traces 22ip, 22im on PCB 20. Each receive signal trace Rx(i)p 32 ip, Rx(i)m 32im has a corresponding receive termination resistor RRXip 33ip, RRXim 33 im at a front end of the receiver IC 30. The receive termination resistor pairs RRXip 33ip, RRXim 33 im are positioned in shunt across the corresponding receive signal trace pairs Rx(i)p 32ip, Rx(i)m 32im, with their common terminal connected to a local reference voltage.
Thus, absent the interposition of a discrete capacitor 21ip, 21im on the PCB across each copper trace 22ip, 22im, the differential signalling traces Tx(i)p 12 ip, Tx(i)m 12im on the transmitter IC 10 would be DC-coupled to the differential signalling traces Rx(i)p 32ip, Rx(i)m 32im on the receiver IC 30.
Such discrete PCB capacitors 21ip, 21im, also referred to as “AC-coupling” capacitors, on the PCB 20, combine with the corresponding receiver termination resistor RRXip 33ip, RRXim 33im at the front end of the receiver IC 30 to form a high-pass filter that allows most of the signal energy arriving along the corresponding copper trace 22ip, 22im to pass, while blocking DC and thus rendering substantially irrelevant the different operating points of the transmitter IC 10 and receiver IC 30.
In some example embodiments, the fact that the AC-coupling capacitors are discrete components facilitates the employ of large capacitance values on the order of 100 nF, to achieve a filter cut-off frequency that is relatively low, on the order of 50 kHz or lower, so as to minimally impair the wide frequency spectrum of the input data stream.
However, as demands for communication bandwidth increases, there is a corresponding increasing pressure to increase the channel density of ICs. In such an environment, the space and cost of interposing discrete AC-coupling capacitors on the PCB 20 becomes increasingly difficult.
One mechanism to dispense with a discrete PCB AC-coupling capacitor, by employing integrated AC-coupling capacitors C1p 34p, C1m 34m on the front-end of the receiver IC 30, is shown in FIG. 2. Such integrated capacitors may be used to achieve signal attenuation by forming a capacitive divider with capacitors C2p 39p, C2m 39m. Capacitors C2p 39p, C2m 39m may be a device element added for the capacitive divider function or can be a proxy for any parasitic capacitance that is present at the receiver 31.
For ease of illustration, only one of the receiver circuits Rx(i) 31i is shown (and the generic subscript i has been omitted throughout), although those having ordinary skill in the art will appreciate that a given receiver IC 30 may employ a plurality of such receiver circuits. Also for ease of illustration, the copper traces 22p, 22m are omitted and the transmit differential signalling traces Txp 12p, Txm 12m are shown directly connected to the receive differential signalling traces Rxp 32p, Rxm 32m. 
In the example of FIG. 2, the single pair of receive termination resistors RRXp 33p, RRxm 33m shown in FIG. 1 is replaced by receive termination resistors R1p 35p, Rim 35m between the corresponding receive signal trace pairs Rxp 32p, Rxm 32m and a common terminal between them. The common terminal between the receive termination resistors R1p 35p, R1m 35p may in some cases be decoupled from a ground point GND 37 by a respective decoupling capacitor Ccm 38. The common terminal between the second pair of receive termination resistors (R2p 36p, R2m 36m) provides an independent receiver DC voltage reference VcmRef 40 for use by the receiver circuit Rx 31. A second set of capacitors C2p 39p, C2m 39m are connected across the corresponding receive signal trace pairs Rxp 32p, Rxm 32m, with the common terminal therebetween connected to the ground point GND 37.
Thus, the DC condition of the receiver circuit Rx 31 remains isolated from the corresponding transmitter circuit Tx 11 by the on-die capacitors C1p 34p, C1m 34m, while the high-pass filter created by the on-die capacitors C1p 34p, C1m 34m, in conjunction with the resistors R2p 36p, R2m 36m, allows most of the signal energy arriving along the corresponding pair of transmit traces 12p, 12m to pass.
Because the capacitance density of on-die capacitors is typically much lower than that of discrete capacitors, achieving a capacitance value using the on-die capacitors C1p 34p, C1m 34m that approaches that of the discrete case would involve the allocation of an impractical amount of silicon area. Further, the parasitic/stray capacitance to GND 37 is in shunt with the termination resistors R1p 35p, R1m 35m. At higher frequencies, the impedance of the parasitic capacitance will approach that of the termination resistor. This will result in a decrease of input impedance with frequency, resulting in worsening of matching between the transmission lines, such that the parasitic capacitance would limit the differential return loss performance that imposes a practical bound on the maximum capacitance value of the on-die capacitors C1p 34p, C1m 34m, to a value of up to 5 orders of magnitude smaller than that of the discrete AC-coupling capacitor(s) shown in FIG. 1.
With the imposition of such a bound, an alternative mechanism to reduce the cut-off frequency is to maximize the resistance of the second pair of resistors R2p 32p, R2m 32m. However, doing so also increases the amount of silicon area consumed. In some cases, a higher cut-off frequency is accepted in order to reduce the resistor size to a manageable dimension.
The trade-off of so doing, however, is the introduction of baseline wander (BLW), which manifests due to a relatively higher cut-off frequency of the high pass filter, with a concomitant reduction in signal-to-noise ratio (SNR) at the receiver. Baseline wander is an effect where the base axis of a signal (if viewed on a screen) appears to wander or move up and down causing the signal to shift from its normal base and resulting in decreased SNR. The baseline wander problem is exacerbated at low data rates.
Because modern wireline transceivers may operate at upwards of data rates of 32 Gb/s, the receiver circuit Rx 31 may be in some example embodiments designed to meet stringent performance constraints at these high data rates, resulting in a relatively small value of the on-die capacitor C1p 34p, C1m 34m. However, in so doing, such receiver circuits Rx 31 may suffer from poor baseline wander performance when operating at legacy rates as low as 125 Mb/s that are still to be supported by such circuits.
A further mechanism to dispense with a discrete PCB AC-coupling capacitor by employing integrated AC-coupling capacitors on the front-end of the receiver IC 30 is discussed in Dong, Y. et al., “Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced Traffics”, Proceedings of the IEEE International Symposium on Circuits and Systems (2007), at pp. 2132-2135 and is generally shown in FIG. 3. This example embodiment differs from that of FIG. 2 in that baseline wander correction circuitry is introduced, in an attempt to mitigate any performance degradation due to baseline wander, especially at low data rates.
As with the example of FIG. 2, the DC condition of the receiver 31 is fully isolated from the transmitter 11 by the on-die capacitors 34p, 34m. 
However, in this example, the baseline wander correction circuitry re-inserts the low-frequency energy lost due to the high-pass filter formed by the combination of the on-die capacitors 34p, 34m with the second pair of receive termination resistors 32p, 32m. The recovered data now passes through a low-pass filter formed from the same components as the high pass filter. As such, it is the inverse. Now the low frequency is introduced in this feedback path, while high frequencies are filtered. Thus, low frequency content is re-introduced, alleviating the problem of baseline wander. The baseline wander correction circuitry comprises a circuit for reconstructing the received data stream and a feedback circuit 44 for restoring the lost energy. In some example embodiments, the equalization circuit may comprise a digitizer 41 for digitizing the received data stream and a decision circuit 42. The decision circuit 42 recovers a clock signal 43 from the received data stream to clock the digitizer 41. The differential outputs of the digitizer 41 are fed in as inputs to the feedback circuit 44 so that lost energy is re-introduced into the receiver circuit, effectively producing current adaptation that reduces the observed baseline wander. The feedback circuit 44 generates the independent receiver DC voltage reference VcmRef 40.
It will be appreciated that the baseline wander correction and control of the differential voltage at the receiver are performed simultaneously by the example embodiment of FIG. 3.
The baseline wander correction circuitry described in FIG. 3 mitigates the resulting baseline wander experienced by these AC-coupled circuits that employ integrated on-die capacitors and thus dispense with discrete AC-coupling capacitors. However, the effectiveness of the baseline wander correction circuitry is dependent upon the data recovery performance of the receiver 30. Thus, it may be seen that there is imposed a co-dependency between the link adaptation that governs the recovery of the received signals, as measured by the error rate, and the baseline wander correction. Such co-dependency may have deleterious effects. Furthermore, because the baseline wander correction in the example embodiment of FIG. 3 relies upon effective data recovery of the received data, the circuitry is dependent on a mechanism to reconstruct the received data stream. Accessing the recovered symbols for this purpose can cost additional power since these are high-speed nodes.